This invention relates to a structure comprising a thin layer of material made up of conductive zones and insulating zones. It also relates to the method of manufacturing such a structure.
Certain components created on the surface of a substrate require, in order to be used, that an electric current is able to pass through the thickness of the substrate, that is to say, in the vertical direction with respect to the plane of the substrate. One may mention as an example components with vertical operation: electroluminescent diodes, laser diodes (in particular, laser diodes with a vertical cavity), photodetectors, hyperfrequency detectors (in particular, Schottky diodes), power components, solar cells. These components are represented diagrammatically in the form of doped substrates, on which, the active or non-active layers are produced by a specific doping operation. As a general rule, the electrical contacts are made on the front facing surface and at the back of the component or at depth.
Power diodes have two contacts: the anode contact on the front face and the cathode contact on the back face. For more sophisticated power components such as the MOSFETs, the IGBTs and the thyristor structures, there is still one contact on the front face and one contact on the back face with one or more contact points at depth. However, for all these types of components, the electrical current passes between the front and rear faces of the device (see for example the synthesis article entitles xe2x80x9cTrends in power semiconductor devicesxe2x80x9d by B. JAYANT BALIGA, that appeared in IEEE Transactions on Electron Devices, Vol. 43, No. 10, October 1996).
One of the techniques used to provide active layers on the substrate is epitaxial growth. This technique consists of causing a material to grow in an ordered manner from a crystalline substrate whilst controlling its composition. Stacks of epitaxiated semiconductor layers with variable doping levels can be produced in this way. If the epitaxiated semiconductor layers are of the same kind as the crystalline substrate, one refers to deposition by homo-epitaxy. If they are of a different kind, then this is deposition by hetero-epitaxy. This technique permits the production of semiconductor layers of very small thickness (a few tens of Angstrom units), of high purity and with interfaces of excellent quality. However, this technique is very expensive and its low rate of deposition does not enable one to obtain semiconductor layers of thickness greater than a few tens of micrometers in an industrial manner. Furthermore, the epitaxy of the layers can only be created if the substrate has crystal parameters which are close to those of the material to be epitaxiated. In effect, if the crystal parameters are not sufficiently close, the limitation to the matching the lattice parameters greatly reduces the good optical and electronic properties of the structures obtained by hetero-epitaxy. Therefore, this severely limits the number and the diversity of the layers that one is able to grow. In particular, one may mention the difficulty in obtaining components from the III-V family of semiconductors on silicon substrates. For certain components, it is of interest to combine the advantages of different semiconductors. By way of example, one can consider the cases of an active layer of GaAs or an active layer of InP on silicon. This configuration allows one to associate the good electronic properties of the GaAs or InP materials at hyperfrequency with a silicon substrate which has the advantage of being more robust, having less weight and which has better thermal conductivity than GaAs. One may also mention the case of a layer of GaN on a SiC substrate, a structure which offers many advantages for electronic power components.
In another field, solar cells for use in space are of great interest. In effect, energy for satellites is generally supplied by means of panels of solar cells. Among the various possibilities for producing solar cells for use in space, one can mention solar cells made of GaAs. The problem of gallium arsenide is its cost and above all its weight and its fragile nature. In order to resolve this problem, it has been proposed to produce solar cells from thin films of GaAs epitaxiated onto a germanium substrate. A great improvement would consist of providing thin films of GaAs or InP on a silicon substrate. This type of structure would allow one to combine the advantages of GaAs (surface properties to create the component constituting the solar cell) and the advantages of silicon as a support (weight three times less than that of GaAs and much less fragile).
In order to produce these structures made up of a thin film, integral with a substrate of a different material, processes other than hetero-epitaxy can be used. In particular, one may mention the methods of bringing semiconductor substrates into contact by bonding them using molecular adhesion or techniques for transferring thin films. The method disclosed by the document FR-A-2 681 472 offers numerous advantages. It allows one to transfer a thin semiconductor film with a large surface area (of a few thousand Angstrom units with a few micrometers of thickness), from its original substrate to the desired support by a combination of ionic implantation (using light ions), bonding by molecular adhesion and an appropriate heat treatment.
This transfer technique has been the subject of other developments. According to document FR-A-2 748 851, the ion implantation step is carried out with an ion dose which is between a minimum dose and a maximum dose. The minimum dose is that from which sufficient micro-cavities will be created to provide weakening of the substrate along the reference plane. The maximum dose, or critical dose is that above which, during the heat treatment step, there is separation of the substrate. The separation step comprises the application of mechanical forces between the two parts of the substrate.
If the thin film defined in the substrate is sufficiently rigid itself (because of its thickness or because of its mechanical properties), after the transfer annealing, one can obtain a self-supporting film. This is what is disclosed in document FR-A-2 738 671.
Document FR-A-2 767 416 discloses that it is possible to lower the annealing temperature if the thermal budget supplied to the substrate during the various steps of the method is taken into account (ion implantation step, possibly a step of bonding the substrate to a stiffener, possible intermediate treatments, an annealing step to allow separation). By the term thermal budget one understands that for a step where thermal energy is supplied (for example during an annealing step), one must not only consider the temperature but the time-temperature couple supplied to the substrate.
This technique is used now for the industrial manufacture of SOI substrates (see the article by A. J. AUBERTON et al., entitled xe2x80x9cSOI materials for ULSI applicationsxe2x80x9d that appeared in Semiconductor International, 1995, Vol. 11, pages 97-104). The feasibility of this technique to III-V semiconductor materials such as GaAs has recently been demonstrated (see the article by E. JALAGUIER et al., entitled xe2x80x9cTransfer of 3 in GaAs Film on Silicon Substrate by Proton Implantation Processxe2x80x9d published in Electronics Letters, Feb. 19, 1998, Vol. 34, No. 4, pages 408-409). For such a structure, made up of a thin film of GaAs on a silicon support, bonding by using an intermediate layer of silicon oxide has been used. The thin layer of GaAs is therefore electrically insulated from the silicon support. In the case of a solar cell constituted in this way, it is necessary to make an electrical connection on the front face and an electrical connection on the back face, electrical connection with the photo-voltaic thin layer being made through the substrate.
One solution to this problem can be found by choosing a conductive interface between the thin layer and its support, this interface then having also to provide the adhesion of the two parts. Several techniques have been suggested to achieve this. They are given below.
It is possible to provide a direct bond between two semiconductor elements which provide a good electrical contact between these two elements. On this subject one can make reference to the following articles:
xe2x80x9cElectrical characteristics of directly-bonded GaAs and InPxe2x80x9d by H. WADA et al., that appeared in Appl. Phys. Lett., 62(7), Feb. 15, 1993;
xe2x80x9cLow-resistance ohmic conduction across compound semiconductor wafer-bonded interfacesxe2x80x9d by F. A. KISH et al., that appeared in Appl. Phys. Lett., 67 (14), Oct. 2, 1995.
The techniques described in these articles are however rather restricting. They frequently demand very good preparation of the surfaces before bonding, often under ultra-vacuum conditions and/or also post-bonding heat treatments at a high temperature (from 600 to 1000xc2x0 C.) under a reducing atmosphere of hydrogen. These conditions are difficult to implement, in particular when the two semiconductor materials have very different coefficients of thermal expansion (for example, GaAs in relation to Si or SiC). In this case, it is necessary to use low temperature bonding.
Another possibility consists of bringing the two semiconductor elements into contact using previously deposited metal layers. This solution is described in the article xe2x80x9cLow Temperature Bonding of Epitaxial Lift-Off Devices with AuSnxe2x80x9d by G. RAINER DOHLE et al., that appeared in IEEE Transactions on Components, Packaging and Manufacturing Technologyxe2x80x94Part B, Vol. 19, No. 13, August 1996.
In addition, a development of the method described in the document FR-A-2 681 472, mentioned above, has been disclosed in document FR-A-2 758 907. This latter document discloses that, under certain conditions, a masking technique can be used to protect sensitive zones of the future thin layer (for example, constituent zones of MOS transistors) from the passage of ions intended to create the micro-cavities. This implies an absence of micro-cavities in the zones of the bombarded substrate corresponding to the masked areas. Despite all this, cleavage of the substrate can be obtained allowing detachment of a thin film if the width of each masked area does not exceed a limiting value that is specified for the material that constitutes the substrate.
One might then think, given the state of the art described above, that the method of transferring a thin semiconductor layer disclosed by the document FR-A-2 681 472 would allow one to obtain a thin layer of GaAs integral with a silicon support using a conductive interface and that an electrical connection would be possible between the thin layer of GaAs and the silicon support. However, the application of this method of transfer has revealed the following problem. The ion implantation step is generally carried out using light ions such as hydrogen ions. It is found that the passage of hydrogen ions in the GaAs has the effect of considerably modifying the resistivity of the region bombarded by these ions. Hence, a region of GaAs with an initial resistivity of the order of 1 mxcexa9xc2x7cm, sees its resistivity reach a value of the order of 105 xcexa9xc2x7cm, after bombardment with hydrogen ions. This phenomenon is due to the hydrogen which has created centers deep within the GaAs. The result is that a film of GaAs epitaxiated onto a thin layer of GaAs transferred onto a silicon support would be electrically insulated from the support.
To remedy this problem, one can consider using species other than hydrogen to carry out the ion implantation. Hydrogen is however preferred for practical reasons. One may also attempt to restore a certain conductivity to the thin layer of GaAs by means of annealing treatments subsequent to the cleavage. However, these annealing treatments imply a break in the progress of the manufacturing process and are not always desirable.
So as to remedy the disadvantages of the prior art, a structure is proposed that is obtained by the method described in document FR-A-2 681 472, this method being modified so that the conductive or semiconductive layer to be transferred, which is a layer capable of being corrupted by the ion bombardment, is locally protected. This protection allows a transferable layer to be provided that has zones with electrical properties that have not been corrupted.
Hence a subject of the invention is a method of manufacturing a thin layer, the thin layer having to provide at least one vertical electrical connection through its entire thickness, the thin layer being made of a conductive or semiconductive material capable of having its electrical properties disrupted when it is subjected to an ion implantation using specified species, the method comprising the following steps:
masking one face of a substrate comprising said material by masking means that define at least one masked area, the size of which does not exceed a limiting dimension specified for said material, this limiting dimension having to permit splitting of the substrate at the time of the subsequent step of cleavage;
ion implantation of the substrate through its masked face by means of said species, the implantation being capable of creating, within the non-masked volume of the substrate and at a depth close to the mean depth of penetration of the species, a layer of micro-cavities defining said thin layer;
possible removal of said masking means
cleavage of the substrate at the level of the layer of micro-cavities in order to obtain said thin layer.
The implanted face of the substrate can be made integral with a support before the cleavage step. It can also be made integral with a support after the cleavage step.
The cleavage step corresponds to a separation of the thin layer and the substrate.
The masking means can comprise deposits of a material capable of preventing penetration of the ions into the substrate during the ion implantation, these deposits being deposited on said face of the substrate. They can also comprise micro-elements deposited on said face of the substrate. These micro-elements can be chosen from among micro-beads and particles.
The masking can be carried out in such a way that the thin layer, retains overall, the electrical properties of the substrate. It can also be created in such a way that the thin layer behaves overall like an insulating layer except for at least one part formed from one zone or several neighboring zones that retain the electrical properties of the substrate. In this case, the part formed by this zone or by these neighboring zones that retain the electrical properties of the substrate can constitute a conductive path or a conductive track.
Integration of the substrate with a support can be achieved by a method chosen between bonding by molecular adhesion and bonding by means of a brazing material, for example a brazing material based on indium.
Before the integration, the method can comprise a step of preparing a conductive interface between said face of the substrate and the support. This step of preparing a conductive interface can comprise the deposition of a metal layer on the face of the substrate and/or on the face of the support, for example, the deposition of a layer of palladium. Associated with this metal layer can be the deposition of conductive metal bonding materials, for example, successive depositions of titanium, nickel and gold. A heat treatment can be carried out in a way to cause the diffusion of the deposited metal layer. The metal material is preferably chosen to react with at least a part of the material of the substrate and/or the support.
This method is advantageously applicable to the manufacture of a structure comprising a thin layer of SiC, GaAs or InP on a support, the ion implantation using hydrogen and/or helium ions. The support can notably be silicon.
Another subject of the invention is a structure comprising a thin layer, the thin layer being a layer of conductive or semiconductive material made insulating by ion implantation except for at least one zone that permits a vertical electrical connection through the entire thickness of the thin layer.
According to a first variant, the thin layer comprises a multitude of zones, these zones being distributed over the whole surface of the thin layer. According to a second variant, the thin layer comprises one zone or a plurality of zones, concentrated in order to constitute at least one conductive path or at least one conductive track.
The thin layer can be integral with a support through the use of an intermediate conductive interface so as to allow electrical connection between these two elements. This conductive interface can be constituted by a metal layer, for example a layer of palladium. Associated with this metal layer can be the deposition of conductive metal bonding materials, for example, successive depositions of titanium, nickel and gold.
The thin layer can also be made integral with a support by using a brazing material, for example a brazing material based on indium.
Advantageously, the semiconductor material of the thin layer is chosen from among SiC, GaAs and InP. The support can notably be silicon.